The present invention relates to a method and apparatus for varying a temperature profile for a wafer of material undergoing plasma processing in order to compensate for other non-temperature effects that cause dimensional variation of etched features across the substrate during plasma processing.
A typical plasma etching apparatus comprises a reactor in which there is a chamber through which reactive gas or gases flow. Within the chamber, the gases are ionized into a plasma, typically by radio frequency energy. The highly reactive ions of the plasma gas are able to react with material, such as a polymer mask on a surface of a semiconductor wafer being processed into integrated circuits (IC""s). Prior to etching, the wafer is placed in the chamber and held in proper position by a chuck or holder, which exposes a top surface of the wafer to the plasma. The chuck provides an isothermal surface and serves as a heat sink for the wafer. There are several types of chucks (also sometimes called susceptors) known in the art. In one type, a semiconductor wafer is held in place for etching by a mechanical clamp. In another type of chuck, a semiconductor wafer is held in place by an electrostatic force generated by an electric field disposed between the chuck and the wafer. The present invention is applicable to both these types of chucks.
In a typical plasma etching operation, the reactive ions of the plasma chemically react with portions of material on a face of the semiconductor wafer. In most cases, it is highly desirable that etched features be uniform to a nearly perfect degree since otherwise the ICs being fabricated will have electronic characteristics that deviate from the norm more than is desirable. Variations in the photolithography process as well as variations in the etching process can cause variation from the ideal in etched feature dimensions. Furthermore, with each increase in the size of wafer diameter, the problem of ensuring uniformity of ICs from within larger and larger wafers becomes more difficult. Variations in the lithography process result in non-ideal dimensions in the photoresist mask, which is laid down on the wafer surface to define the etching pattern. This deviation from ideal can be viewed as an overall shift of the mean feature dimensions as well as the variation among the numerous features throughout the wafer surface.
It is common practice to define test images in multiple locations over the wafer surface, and these test images are often referred to as xe2x80x9ccritical dimension featuresxe2x80x9d or xe2x80x9cCD""sxe2x80x9d for short. A measurement of these CD""s after the photo imaging process can be used to determine the xe2x80x9cCD shiftxe2x80x9d from the lithography operation. Likewise a measurement of the CD""s in the photoresist can be compared to the etched features that they define after the etching process, and a CD shift can be calculated and attributed to the etch process. It is desirable that these CD shifts be stable from wafer to wafer and uniform over a wafer surface, so that a simple correction bias to the original mask image can be used to compensate out the systematic CD shift.
Historically such global shift correction was feasible, but with the reduction in IC minimum feature dimensions to 0.10 microns and below, the shift is no longer sufficiently controllable, either globally or within a wafer, making the previous simple mask correction inadequate. What is required is a means to measure CD shift in the photoresist mask, perhaps by lot or even by individual wafer, and use this information to alter the CD shift within the etch process.
It has been known that plasma etching is a combination process of both etching and deposition. The deposition process on the feature sidewalls allows control of the feature width. This process is temperature dependent but at the larger dimensions of the past, for example, greater than 2 micron, the effect was not of significance with regard to linewidth control. However, as dimensions fall below about 0.1 micron, this temperature dependence has come to have a significant effect upon feature width control.
Accordingly, a need exists for a method and apparatus for controlling the temperature of semiconductor wafers during reactive ion etching and similar processes based on the particular feature dimensions on a wafer. A primary purpose of the present invention is to solve these needs and provide further, related advantages.
An etching system for etching a wafer of a material has a measuring device, an etching chamber, and a controller. The measuring device measures the critical dimension test feature (CD) along the profile of the wafer at a plurality of preset locations. The etching chamber receives the wafer from the measuring device. The etching chamber includes a chuck supporting the wafer and a plurality of heating elements disposed within the chuck. Each heating element is positioned adjacent to each preset location on the wafer. The etching system controller is coupled to the measuring device to receive the actual measured CD""s for a particular wafer. The etching system controller is also connected to the plurality of heating elements. The controller adjusts the temperature of each heating element during a process to reduce the variation of critical dimensions among the plurality of preset locations by using temperature dependent etching characteristics of the etch process to compensate for CD variation introduced by the lithography process preceding the etch process.